The present invention relates to a data processor with an internal (built-in) memory operable to perform specified data processing operations, such as analytical operations and numerical arithmetic operations, while reading/writing data (including programs such as instructions) from/into the internal memory.
A so-called memory-incorporated data processor, in which a processing unit and an internal memory (a DRAM (dynamic random access memory) in particular) are formed on a single chip, has recently been developed. In such an arrangement, data can be transferred at a considerably high bit rate, because the processing unit and the internal memory can be connected together via a short data bus having a broad bit width. Accordingly, high-speed data processing can be performed while making full use of the performance of the processing unit.
For example, when such a data processor is applied to a video controller, the internal memory may be used as a frame buffer for video. The video data stored in the frame buffer can be processed at high speed in the processing unit and then supplied through a D/A (digital-to-analog) converter to an external monitor. This makes it possible to provide smooth video images.
In some applications of the data processor, however, required storage capacity cannot be obtained by the internal memory alone. For instance, if the number of colors or the size of a monitor is increased in image processing applications, then the internal memory alone cannot provide sufficient storage capacity for constructing a frame buffer. As an imaginable solution, an internal memory having a relatively great storage capacity may be mounted beforehand in order to cope with various cases. However, such a solution is not cost-effective. Thus, in such a case, an external memory is optionally added, thereby obtaining a desired storage capacity by using the internal and external memories in combination.
However, if such an external memory is added, then a memory system is made up of the internal and the external memories. Thus, the overall performance of the memory system is determined by the access rate of the external memory after all. Although the internal memory is provided, it is hard to improve the overall performance, resulting in several problems. For example, in image processing applications, video image rendering rate becomes adversely low and motions of the image become undesirably awkward.
The objective of the present invention is providing a data processor, incorporating an internal memory allowing for the improvement of overall memory system performance, for a memory system made up of an internal memory and an external memory having an operating speed lower than that of the internal memory.
In order to solve the above-described problem of the prior art techniques, the present invention provides an improved data processor. In the data processor of the present invention, a memory control unit for performing read/write operations on an external memory and a buffer part for storing data from an internal memory or from the external memory are controllably coupled to a processing unit, thereby carrying out data exchange between the internal memory and the external memory by temporarily storing, in the buffer part, data from the internal memory or from the external memory.
In the data processor of the present invention, either data obtained from the external memory through the memory control unit or data obtained from the internal memory is temporarily stored in the buffer part, and physical data exchange can be carried out between the internal memory and the external memory. Thus, it is possible to store data requiring fast processing in the internal memory and data not requiring so fast processing in the external memory, respectively. As a result, the overall memory system performance can be improved when degrees of necessity of high speed processing are variable among access areas (memory regions) of a memory system. In general, in the case of transferring data between an external memory (main memory) and an internal memory (cache memory), data in the internal memory is copied to the external memory without applying any modification thereto. Also, even in the case of swapping data between an internal memory (main memory) and an external memory (a magnetic disk device) in a virtual memory system, data in the internal memory is also copied to the external memory without applying any modification thereto. In other words, in both of these cases, a region corresponding to the internal memory always exists in the external memory. However, in the data processor of the present invention, no such regions corresponding to the internal memory exist in the external memory. Therefore, a sum of the storage capacity of the external memory and that of the internal memory can be used as a memory space without wasting any memory region.
The present invention is also characterized in that the processing unit includes an address management part for controlling addresses of said internal and external memories. When data exchange is performed between said internal memory and the external memory, address allocations corresponding to the data exchange are exchanged by the address management part. Thus, even if data has been exchanged between arbitrary physical addresses, the logical addresses remain unchanged in spite of such data exchange. Therefore, it is not necessary to reform a logical memory map of the memory system.
In one embodiment of the present invention, the memory control unit may be provided with an additional function of performing data conversion in parallel or in series between the internal memory and the external memory. And the processing unit and the memory control unit may be coupled together via a data bus having the same width as a width of a data bus between the internal memory and the processing unit. In such arrangement, the processing unit need not convert data, provided from the internal memory through a data bus having a width and coupling the processing unit to the internal memory, into data corresponding to a width of a data bus between the processing unit and the memory control unit, in order to output the data to the memory control unit. As a result, the load of the processing unit can be lightened, and a data bus having the same width can be used in common between the processing unit and the internal memory and between the processing unit and the memory control unit.
In another embodiment of the present invention, the memory control unit or the processing unit may be provided with a comparator for comparing a data item from the internal memory with another data item from the external memory. If the comparator indicates that these data items are different from each other, the data items may be written into the internal memory or into the external memory, thereby exchanging the data items between the internal memory and the external memory. In such an arrangement, if the comparator indicates that these items are the same, a write cycle need not be activated with respect to the internal and external memories. Thus, the processing load and time required for performing data exchange can be reduced.
In still another embodiment, the memory control unit or the processing unit may be provided with an arithmetic part for performing data arithmetic operations on the data from the internal and external memories. For example, if the data processor of the invention is applied to an MPEG (moving picture experts group) encoder and I/B/P pictures stored in the internal memory and in the external memory are different from each other, it is possible to perform inter-picture data arithmetic operations when data is exchanged between the internal memory and the external memory. As a result, it is possible to store post-arithmetic picture data in at least one of the memories during the data exchange.
In still another embodiment, the data exchange may be carried out with respect to a memory region having a specified storage capacity. And data exchanges may be carried out between the internal memory and the external memory in order that memory regions frequently accessed by the processing unit and memory regions infrequently accessed by the processing unit are located in the internal memory and in the external memory, respectively. In such arrangement, if some memory regions of a memory system are locally accessed more frequently than other regions during a specified period of time, then the memory regions frequently accessed can be located in the internal memory at an arbitrary point in time. As a result, the overall memory system performance can be improved.
In still another embodiment, the processing unit or the memory control unit may be provided with tag memories. Each of the tag memories stores a value indicating how may times each memory region of the internal memory or the external memory is accessed. Data exchange may be carried out between each memory region of the internal memory and an associated memory region of the external memory by making reference to a corresponding value stored in the tag memory. In such an arrangement, if counting up is carried out in each of the tag memories provided for the respective memory regions every time each memory region is accessed, then it is easy to know as a whole how many times each memory region has been accessed. Accordingly, data exchange can be carried out with higher precision on the basis of a memory region.
In still another embodiment, each of tag memories may include: a tag comparator part for receiving a memory address from the processing unit to decide which memory region is an object of access; and a memory count part for receiving a trigger signal from the tag comparator part to perform count-up operations. In such an arrangement, if a memory address from the processing unit is provided to the tag comparator part, then count-up operations are automatically performed in the memory count part. Accordingly, the processing unit or the memory control unit need not examine memory addresses one by one to decide which memory region is to be accessed and store a value indicating how many times the memory region has been accessed. As a result, the processing load of the processing unit or memory control unit can be lightened.
In still another embodiment, the processing unit or the memory control unit may be provided with a buffer memory having a storage capacity greater than that of the memory region. Data exchange may be carried out between the internal memory and the external memory by temporarily writing data into the buffer memory. In such an arrangement, data can be exchanged between memory regions by: (i) continuously reading out data from a memory region in one of the internal and external memories and storing the data in the buffer memory; (ii) continuously writing data, stored in a memory region of the other memory, into the memory region, from which the data has been read out in (i); and (iii) continuously writing the data stored in the buffer memory into the memory region of the other memory. As a result, data can be exchanged quickly.
In still another embodiment, a plurality of such buffer memories may be provided. In such an arrangement, it is possible to store data from the internal memory and data from the external memory in the respective buffer memories by simultaneously accessing the internal and external memories. As a result, a time required for data exchange can be reduced.
In still another embodiment, data may be exchanged between the internal memory and the external memory by using a blank memory region in the external memory. In such an arrangement, data to be exchanged is temporarily written into the existing external memory. As compared with the cases of using a buffer memory, data is exchanged at a lower speed. However, the costs can be reduced even when a buffer memory is separately provided.
In still another embodiment, the processing unit or the memory control unit may be provided with identification bits for blank memory regions corresponding to respective memory regions of the external memory. In such an arrangement, the processing unit or the memory control unit can know blank memory regions of the external memory by referring to the code of the identification bits.
In still another embodiment, the memory control unit may have a plurality of access ports for accessing a plurality of external memories. And data exchange may be carried out between the external memories respectively coupled to the access ports and said internal memory. In such an arrangement, the overall memory system performance can be improved by mapping data requiring high-speed processing or specific data frequently accessed into the internal memory in memory systems of a larger size.
In still another embodiment, the data exchange is preferably carried out when data, which has been received from the internal memory or from the external memory as an object of data exchange, is being output to an external unit. In such an arrangement, while the data received from one of the internal and external memories is being output, the other memory may be usually accessed at any arbitrary addresses. Thus for example, a sequence may be performed in which (i) data to be exchanged is read from one of the memories, temporarily stored in the buffer part and then output to an external unit, (ii) data to be exchanged in the other memory is simultaneously written into the one memory, and then (iii) the data stored in the buffer part is written into the other memory. This considerably reduces overhead involved by data exchange, thereby enhancing the effects of the present invention.
The present invention provides a data processing system, in which a plurality of data processors having the above-described configuration are coupled together through the memory control units thereof and data exchange is carried out between internal memories of the data processors. In the data processing system of the present invention, data can be exchanged between the internal memories in order that data required by the processing units of the data processors are mapped to the internal memories associated with the processing units. As a result, the overall data processing performance is improved.
The present invention also provides a data processing system. In the data processing system, memory control units of a plurality of data processors having the above-described configuration are provided with a plurality of access ports for accessing an external unit. The data processors are coupled together through the access ports thereof, and data is exchanged between internal memories of the data processors. In this data processing system, since the data processors are coupled together via a plurality of data buses, it is possible to simultaneously read/write data between data processors, in which data should be exchanged through these data buses.